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digital input 2 w class-d audio power amplifier data sheet SSM2519 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features filterless digital input class-d amplifier standalone operation or i 2 c control serial digital audio interface supports common formats: i 2 s, left justified, right justified, tdm1-16, and pcm 2.31 w into 4 and 1.35 w into 8 at 5 v supply with 1% thd + n available in 12-ball 1.4 mm 1.7 mm 0.4 mm pitch wlcsp efficiency 90% at full scale into 8 9 mw loaded idle power at 1.8 v/3.6 v snr = 98 db, a-weighted psrr = 80 db at 217 hz, dither input supports wide range of sample rates: 8.0 khz to 48.0 khz autosample rate and mclk rate detection no bclk required for operation 2.5 v to 5.5 v pv dd speaker operating supply voltage 1.5 v to 3.6 v v dd operating voltage pop and click suppression short-circuit and thermal protection with autorecovery smart power-down when no input signal detected power-on reset low emi emissions applications mobile phones portable media players laptop pcs wireless speakers portable gaming navigation systems functional block diagram figure 1. general description the SSM2519 is a digital input, class-d power amplifier that com- bines a digital-to-analog converter (dac) and a sigma-delta (-) class-d modulator. this unique architecture enables extremely low, real-world power consumption from digital audio sources with excellent audio performance. the SSM2519 is ideal for power sensitive applications, such as mobile phones and portable media players, where system noise can corrupt small analog signals such as those sent to an analog input audio amplifier. using the SSM2519 , audio data can be transmitted to the amplifier over a standard digital audio serial interface, thereby significantly reducing the effect of noise sources such as gsm interference or other digital signals on the transmitted audio. the closed-loop digital input design retains the benefits of a completely digital amplifier, yet enables very good psrr and audio performance. the three-level, - class-d modulator is designed to provide the least amount of emi interference, the lowest quiescent power dissipation, and the highest audio efficiency without sacrificing audio quality. input is provided via a serial audio interface, programmable to accept all common audio formats including i 2 s, left justified (lj), right justified (rj), tdm, and pcm. the SSM2519 is designed to operate with or without a control interface such as i 2 c, which is typically required for this type of device. several control pins offer selection of operation when i 2 c control is not used. the SSM2519 can accept a variety of input mclk frequencies and can use bclk as the clock source in some configurations. both the input sample rate and mclk rates are automatically detected. the architecture of the SSM2519 provides a solution that offers lower power and higher performance than existing dac plus class-d solutions. its digital interface also offers a better system solution for other products whose sole audio source is digital, such as wireless speakers, laptop pcs, portable digital televisions, and navigation systems. the SSM2519 is specified over the industrial temperature range of ?40 ? c to +85 ? c. it has built-in thermal shutdown and output short-circuit protection. it is available in a 12-ball, 1.4 mm 1.7 mm wafer level chip scale package (wlcsp). SSM2519 10750-001 mclk lrclk v dd gnd pvdd bclk sdata sd power-on reset clocking power control i 2 c gain/sda out+ out? i 2 s digital filtering volume/gain dac - ? class-d modulator full bridge power stage lr_format/scl www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? performance specifications ......................................................... 3 ? power supply requirements ....................................................... 4 ? digital input/output .................................................................... 4 ? digital timing ............................................................................... 4 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 12 ? overview ...................................................................................... 12 ? standalone and i 2 c operational mode ................................... 12 ? master and bit clock .................................................................. 12 ? digital input serial audio interface ......................................... 13 ? channel mapping ....................................................................... 13 ? power supplies ............................................................................ 13 ? power control ............................................................................. 14 ? power-on reset/voltage supervisor ....................................... 14 ? low power modes ...................................................................... 14 ? volume control .......................................................................... 14 ? analog gain ................................................................................ 14 ? fault detection and recovery .................................................. 14 ? digital audio formats ................................................................... 15 ? stereo mode ................................................................................ 15 ? tdm, 50% duty cycle mode ................................................... 15 ? tdm, pulse mode ...................................................................... 15 ? pcm, multichannel mode ........................................................ 16 ? pcm, mono mode ..................................................................... 16 ? i 2 c configuration interface .......................................................... 17 ? overview ..................................................................................... 17 ? register summary .......................................................................... 19 ? register details ............................................................................... 20 ? software reset and master software power-down control register ........................................................................................ 20 ? edge speed, power, and clocking control register .............. 21 ? serial audio interface and sample rate control register .... 22 ? serial audio interface control register .................................. 23 ? channel mapping control register ......................................... 24 ? volume control register ........................................................... 25 ? gain and mute control register .............................................. 26 ? fault control register ................................................................ 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 28 ? revision history 7/12revision 0: initial version www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 3 of 28 specifications all conditions at pv dd = 5.0 v; v dd = 1.8 v; f s = 48 khz; mclk = 128 f s ; t a = 25 o c; r l = 8 + 15 h; default i 2 c settings; volume control 0 db setting, unless otherwise noted. performance specifications table 1. parameter symbol test conditions/comments min typ max unit device characteristics output power p out r l = 4 , thd + n = 1%, f = 1 khz, bw = 20 khz, pv dd = 5.0 v 2.31 w r l = 4 , thd + n = 10%, f = 1 khz, bw = 20 khz, pv dd = 5.0 v 2.75 w r l = 8 , thd + n = 1%, f = 1 khz, bw = 20 khz, pv dd = 5.0 v 1.35 w r l = 8 , thd + n = 10%, f = 1 khz, bw = 20 khz, pv dd = 5.0 v 1.68 w r l = 4 , thd + n = 1%, f = 1 khz, bw = 20 khz, pv dd = 3.6 v 1.13 w r l = 4 , thd + n = 10%, f = 1 khz, bw = 20 khz, pv dd = 3.6 v 1.4 w r l = 8 , thd + n = 1%, f = 1 khz, bw = 20 khz, pv dd = 3.6 v 0.69 w r l = 8 , thd + n = 10%, f = 1 khz, bw = 20 khz, pv dd = 3.6 v 0.85 w r l = 4 , thd + n = 1%, f = 1 khz, bw = 20 khz, pv dd = 2.5 v 0.48 w r l = 4 , thd + n = 10%, f = 1 khz, bw = 20 khz, pv dd = 2.5 v 0.6 w r l = 8 , thd + n = 1%, f = 1 khz, bw = 20 khz, pv dd = 2.5 v 0.31 w r l = 8 , thd + n = 10%, f = 1 khz, bw = 20 khz, pv dd = 2.5 v 0.39 w efficiency p out = 2 w, 4 , pv dd = 5.0 v 84 % p out = 1.4 w, 8 , pv dd = 5.0 v, normal operation 90.2 % total harmonic distortion plus noise thd + n p out = 1 w into 8 , f = 1 khz, pv dd = 5.0 v 0.03 % p out = 0.5 w into 8 , f = 1 khz, pv dd = 3.6 v 0.03 % average switching frequency f sw 305 khz differential output offset v oos 1 mv power supply rejection ratio psrr dc pv dd = 2.5 v to 5.0 v 70 82 db psrr gsm v ripple = 100 mv rms at 217 hz, dither input 80 db supply current, pvdd i pvdd dither input, 8 + 15 h load, pv dd = 5.0 v 2.64 ma dither input, 8 + 15 h load, pv dd = 3.6 v 2.24 ma dither input, 8 + 15 h load, pv dd = 2.5 v 2.02 ma dither input, 8 + 15 h load, pv dd = 3.6 v (dac_lpm = 0 and amp_lpm = 0) 2.5 ma hardware shutdown 200 na supply current, vdd i vdd dither input, v dd = 3.3 v 1.14 ma dither input, v dd = 1.8 v 0.6 ma software shutdown, clock present, v dd = 1.8 v 86 a software shutdown, clock removed, v dd = 1.8 v 5 a hardware shutdown 200 na output noise voltage e n pv dd = 5.0 v, f = 20 hz to 20 khz, dither input, a-weighted 37 v pv dd = 3.6 v, f = 20 hz to 20 khz, dither input, a-weighted, gain = 3.6 v 41 v signal-to-noise ratio snr a-weighted reference to 0 dbfs, pv dd = 5.0 v 98 db closed-loop gain gain 0 dbfs input, btl output, f = 1 khz gain = 5.0 v 4.94 v pk gain = 4.2 v 4.21 v pk gain = 3.6 v 3.69 v pk gain = 2 v 1.98 v pk www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 4 of 28 power supply requirements table 2. parameter min typ max unit pv dd 2.5 3.6 5.5 v v dd 1.5 1.8 3.6 v digital input/output table 3. parameter min typ max unit test conditions/comments input voltage high (v ih ) 0.7 v dd 3.6 v mclk, bclk, lrclk, sdata 1.35 5.5 v sd , sda, scl low (v il ) ?0.3 +0.3 v dd v mclk, bclk, lrclk, sdata ?0.3 +0.35 v sd , sda, scl input leakage current high (i ih ) 1 a excluding mclk low (i il ) 1 a excluding mclk and bidirectional pin mclk input leakage current high (i ih ) 3 a low (i il ) 3 a input capacitance 5 pf digital timing all timing specifications are given for the default setting (i 2 s mode) of the serial input port. table 4. limit parameter min max unit description master clock t mp 74 136 ns mclk period, 256 f s mode (mcs = b0010) t mp 148 271 ns mclk period, 128 f s mode (mcs = b0001) serial port t bil 40 ns bclk low pulse width t bih 40 ns bclk high pulse width t lis 10 ns setup time from lrclk or sdata edge to bclk rising edge t lih 10 ns hold time from bclk rising edge to lrclk or sdata edge t sis 10 ns sdata setup time to bclk rising t sih 10 ns sdata hold time from bclk rising i 2 c port f scl 400 khz scl frequency t sclh 0.6 s scl high t scll 1.3 s scl low t scs 0.6 s setup time; relevant for repeated start condition t sch 0.6 s hold time; after this period, the first clock is generated t ds 100 ns data setup time t scr 300 ns scl rise time t scf 300 ns scl fall time t sdr 300 ns sda rise time t sdf 300 ns sda fall time t bft 0.6 s bus-free time (time between stop and start) www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 5 of 28 digital timing diagrams figure 2. serial input port timing figure 3. i 2 c port timing t sis t sih t sis t sih t lih t bp t bih bclk lrclk sdata left-justified mode sdata i 2 c-justified mode sdata right-justified mode t bil t lis t sis t sih t sis t sih msb msb msb lsb msb ? 1 10750-003 t sch t scs t bft t scf t ds t scll t scr t sclh t sch stop condition start condition s d a scl 10750-004 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 6 of 28 absolute maximum ratings absolute maximum ratings apply at 25c, unless otherwise noted. table 5. parameter rating pvdd supply voltage ?0.3 v to 6 v vdd supply voltage ?0.3 v to 3.6 v input voltage (mclk, bclk, sd , lrclk, lr_format, gain, sdata) ?0.3 v to 3.6 v esd susceptibility 4 kv storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +165c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to 7absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 6. thermal resistance package type ja unit 12-ball, 1.4 mm 1.7 mm wlcsp 56.1 c/w esd caution www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 7 of 28 pin configuration and function descriptions figure 4. pin configurationtop view table 7. pin function descriptions ball number pin name function 1 description a1 out+ o amplifier output positive a2 out? o amplifier output negative a3 mclk i serial audio interface master clock b1 pvdd p 2.5 v to 5.5 v amplifier power b2 vdd p 1.5 v to 3.6 v digital and analog power b3 bclk i i 2 s bit clock/generated bclk rate select c1 gnd p ground c2 sd i power-down controlactive low c3 lrclk i i 2 s left/right frame clock d1 lr_format/scl i left/right channel selection and serial format selection/i 2 c clock d2 gain/sda i/o digital and analog gain selection/i 2 c serial data d3 sdata i i 2 s serial data 1 i = input, o = output, p = power. SSM2519 top view (ball side down) not to scale out+ out? mclk pvdd vdd bclk gnd sd lrclk lr_format/ scl gain/ sda sdata 10750-002 1 a b c d 23 ball a 1 indicator www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 8 of 28 typical performance characteristics figure 5. thd + n vs. output power into 8 , 5.0 v gain setting figure 6. thd + n vs. output power into 4 , 5.0 v gain setting figure 7. thd + n vs. frequency into 8 , pv dd = 5.0 v figure 8. thd + n vs. output power into 8 , 3.6 v gain setting figure 9. thd + n vs. output power into 4 , 3.6 v gain setting figure 10. thd + n vs. frequency into 4 , pv dd = 5.0 v 0.01 1 0.1 10 100 0.001 0.01 0.1 1 10 thd + n (%) 2.5v 3.6v 5v p out (w) 10750-005 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) p out (w) 2.5v 3.6v 5v 10750-006 0.001 0.01 0.1 1 10 100 1k 10k 100k thd + n (%) frequency (hz) 10750-007 250mw 500w 1w 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 thd + n (%) p out (w) 2.5v 3.6v 5v 10750-008 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 thd + n (%) p out (w) 2.5v 3.6v 5v 10750-009 frequency (hz) 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) 10750-010 500mw 1w www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 9 of 28 figure 11. thd + n vs. frequency into 8 , pv dd = 3.6 v figure 12. thd + n vs. frequency into 4 , pv dd = 3.6 v figure 13. thd + n vs. frequency into 8 , pv dd = 2.5 v figure 14. thd + n vs. frequency into 4 , pv dd = 2.5 v figure 15. quiescent current vs. supply voltage pv dd figure 16. quiescent current vs. supply voltage v dd 0.001 0.01 0.1 1 10 100 1k 10k 100k thd + n (%) frequency (hz) 10750-111 500mw 250mw 125mw 10750-112 frequency (hz) 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) 500mw 250mw 10750-113 frequency (hz) 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) 62.5mw 125mw 250mw 10750-114 frequency (hz) 0.001 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) 250mw 125mw 10 3 2.5 3.0 3.5 4.0 5.0 4.5 quiescent current (ma) pv dd (v) 10750-115 4 5 6 7 8 9 no load 8 ? 4 ? 1.8 0 1.4 3.6 quiescent current (ma) v dd (v) 10750-116 8khz 24khz 48khz 0.3 0.6 0.9 1.2 1.5 1.61.82.02.22.42.62.83.03.23.4 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 10 of 28 figure 17. quiescent current vs. supply voltage v dd figure 18. maximum output power vs. pv dd (f in = 1 khz, r l = 8 ) figure 19. maximum output power vs. pv dd (f in = 1 khz, r l = 4 ) figure 20. power supply current vs. p out , 4 figure 21. class-d efficiency vs. p out , 4 figure 22. power supply current vs. p out , 8 1.8 0 1.4 3.6 quiescent current (ma) v dd (v) 10750-117 0.3 0.6 0.9 1.2 1.5 1.61.82.02.22.42.62.83.03.23.4 2.0 1.5 1.0 0.5 0 2.5 3.0 3.5 5.0 4.5 4.0 output power (w) pv dd (v) 10750-118 thd + n = 10% thd + n = 1% 3.0 1.5 2.0 2.5 1.0 0.5 0 2.5 3.0 3.5 5.0 4.5 4.0 output power (w) pv dd (v) 10750-119 thd + n = 10% thd + n = 1% 0.8 0 03.0 power supply current (a) p out (w) 10750-120 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.5 1.0 1.5 2.0 2.5 2.5v 3.6v 5v 100 0 02.8 efficiency (%) p out (w) 10750-121 20 40 60 80 0.4 0.8 1.2 1.6 2.0 2.4 2.5v 3.6v 5v 0.8 0 03.0 power supply current (a) p out (w) 10750-122 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.5 1.0 1.5 2.0 2.5 2.5v 3.6v 5v www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 11 of 28 figure 23. class-d efficiency vs. p out , 8 figure 24. output spectrum, 100 mw, 8 figure 25. psrr vs. frequency 100 0 01.5 efficiency (%) p out (w) 10750-123 20 40 60 80 0.30.60.91.2 2.5v 3.6v 5v 0 ?180 10 100 1k 10k 100k output spectrum (dbv) frequency (hz) 10750-024 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 2.5v 3.6v 5v ?100 0 10 100 1k 10k 100k psrr (db) frequency (hz) 10750-025 pvdd = 5v pvdd = 3.6v pvdd = 2.5v ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 12 of 28 theory of operation overview the SSM2519 is a fully integrated digital switching audio amplifier. the SSM2519 receives digital audio inputs and produces the pdm differential switching outputs using an internal power stage. the part has built-in protections against overtemperature as well as overcurrent. the SSM2519 also has built-in soft turn-on and soft turn-off for pop and click suppression. standalone and i 2 c operational mode the SSM2519 supports both standalone and i 2 c control modes. the setting on the sd pin determines which mode is used. table 8. sd pin settings sd pin operation tie to vdd through 20 k i 2 c connect to vdd without 20 k standalone mode connect to gnd (shorted or with 20 k) shutdown mode master and bit clock the SSM2519 requires an external clock present at the mclk input pin to operate. this clock must be fully synchronous with the incoming digital audio on the serial interface. internal to the ic, a clock frequency of 2.048 mhz to 24.576 mhz is required. this internal clock is derived from the external mclk by dividing, passing through, or doubling in frequency the external mclk signal. different rates for mclk are supported at different sample rates. refer to table 9 for all available options. the mclk rate as well as sample rate can be automatically detected by setting the amcs and asr bits in register 0x01, or they can be manu- ally set (mcs bits in register 0x00, and fs bits in register 0x02) if amcs or asr is cleared. when in standalone mode or in i 2 c mode and auto clock rate detection is enabled (register 0x01, bit 1, amcs = 1), the internal clock generation circuitry is automatically configured. when autosample rate detection is disabled (amcs = 0), the mcs bits in register 0x00 must be set with the correct value to generate the internal clock. when the SSM2519 has entered its power-down state, it is possible to gate this clock to conserve additional system power. however, a master clock must be present for the audio amplifier to operate. if the serial interface bit clock (bclk) is in the range of acceptable internal master clock frequencies (between 2.048 mhz and 6.144 mhz), it can serve as both master clock and the bit clock. setting no_bclk (bit 5 of register 0x00) routes the signal on the mclk pin to serve as the internal bit clock as well. in this case, tie the bclk pin to ground. table 9. supported mclk rate for different sample frequencies sample rates supported mclk ra tes supported mclk frequencies 8 khz to 12 khz 256 f s /512 f s /1024 f s /1536 f s /2048 f s 2.048 mhz to 24.576 mhz 16 khz to 24 khz 128 f s /256 f s /512 f s /768 f s /1024 f s 2.048 mhz to 24.576 mhz 32 khz to 48 khz 64 f s /128 f s /256 f s /384 f s /512 f s 2.048 mhz to 24.576 mhz 8 khz to 12 khz 400 f s /800 f s /1600 f s 3.2 mhz to 19.2 mhz 16 khz to 24 khz 200 f s /400 f s /800 f s 3.2 mhz to 19.2 mhz 32 khz to 48 khz 100 f s /200 f s /400 f s 3.2 mhz to 19.2 mhz www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 13 of 28 table 10 . master clock select (mcs) bit se ttings: mclk, ratio, and frequency input sample rate ratio/ mclk setting 0, b0000 setting 1, b0001 setting 2, b0010 setting 3, b0011 setting 4, b0100 setting 5, b0101 setting 6, b0110 setting 7, b0111 setting 8, b1000 8 khz ratio 256 f s 1 512 f s 1024 f s 1536 f s 2048 f s 3072 f s 400 f s 800 f s 1600 f s mclk 2.048 mhz 4.096 mhz 8.192 mhz 12.288 mhz 16. 384 mhz 24.576 mhz 3.20 mhz 6.40 mhz 12.80 mhz 11.025 khz ratio 256 f s 1 512 f s 1024 f s 1536 f s 2048 f s 3072 f s 400 f s 800 f s 1600 f s mclk 2.822 mhz 5.6448 mhz 11.2896 mhz 16.9344 mhz 22.5792 mhz 33.8688 mhz 4.41 mhz 8.82 mhz 17.64 mhz 12 khz ratio 256 f s 1 512 f s 1024 f s 1536 f s 2048 f s 3072 f s 400 f s 800 f s 1600 f s mclk 3.072 mhz 6.144 mhz 12.288 mhz 18.432 mhz 24. 576 mhz 38.864 mhz 4.80 mhz 9.60 mhz 19.20 mhz 16 khz ratio 128 f s 1 256 f s 384 f s 768 f s 1024 f s 1536 f s 200 f s 400 f s 800 f s mclk 2.048 mhz 4.096 mhz 8.192 mhz 12.288 mhz 16. 384 mhz 24.576 mhz 3.20 mhz 6.40 mhz 12.80 mhz 22.05 khz ratio 128 f s 1 256 f s 512 f s 768 f s 1024 f s 1536 f s 200 f s 400 f s 800 f s mclk 2.822 mhz 5.6448 mhz 11.2896 mhz 16.9344 mhz 22.5792 mhz 33.8688 mhz 4.41 mhz 8.82 mhz 17.64 mhz 24 khz ratio 128 f s 1 256 f s 512 f s 768 f s 1024 f s 1536 f s 200 f s 400 f s 800 f s mclk 3.072 mhz 6.144 mhz 12.288 mhz 18.432 mhz 24. 576 mhz 38.864 mhz 4.80 mhz 9.60 mhz 19.20 mhz 32 khz ratio 64 f s 1 128 f s 256 f s 384 f s 512 f s 768 f s 100 f s 200 f s 400 f s mclk 2.048 mhz 4.096 mhz 8.192 mhz 12.288 mhz 16. 384 mhz 24.576 mhz 3.20 mhz 6.40 mhz 12.80 mhz 44.1 khz ratio 64 f s 1 128 f s 256 f s 384 f s 512 f s 768 f s 100 f s 200 f s 400 f s mclk 2.822 mhz 5.6448 mhz 11.2896 mhz 16.9344 mhz 22.5792 mhz 33.8688 mhz 4.41 mhz 8.82 mhz 17.64 mhz 48 khz ratio 64 f s 1 128 f s 256 f s 384 f s 512 f s 768 f s 100 f s 200 f s 400 f s mclk 3.072 mhz 6.144 mhz 12.288 mhz 18.432 mhz 24. 576 mhz 38.864 mhz 4.80 mhz 9.60 mhz 19.20 mhz 1 when using mcs = 0/64 f s mode, the chip automatically operates in low power mode. digital input serial audio interface it is capable of receiving stereo i 2 s, left justified, or right justified data. mono, stereo, and multichannel pcm/tdm interface formats are available. the data and interface formats are selected by adjusting the sdata_fmt and sai bits in register 0x02. note that, when operating in right justified mode, the proper data width must be chosen. the bclk signal does not have to be provided to the SSM2519 . it can internally generate the appropriate bclk signal. to operate without a bclk, the bclk pin should be tied to vdd or gnd to select the appropriate bclk rate for the sdata input. table 11. bclk pin connection options bclk pin generation bclk rate connected to external clock source external any tied to vdd internal 16 bit clocks/channel tied to gnd internal 32 bit clocks/channel when the SSM2519 is set up in standalone mode, a subset of serial interface formats are available. selection of these serial formats and input channel are determined by the lr_format pin. table 12. lr_format pin configuration controls lr_format pin configuration serial format/channel select tie to vdd i 2 s/left channel tie to vdd through 150 k special gain case 1 (i 2 s/left channel) tie to vdd through 47 k pcm/left channel tie to vdd through 15 k lj/left channel tie to gnd i 2 s/right channel 1 see table 14. channel mapping stereo audio formats and tdm formats with two, four, eight, or 16 channels are available. in these modes, the amplifier audio can be chosen from any of the available tdm slots using the ch_sel bits in register 0x04. for most digital interface formats, many of these options are not present. for example, in stereo modes, only channel 0 and channel 1 are valid, and in four-slot tdm mode, only channe l 0, channel 1, channel 2, and channel 3 are valid. power supplies the SSM2519 has two internal power supplies that must be provided. pvdd supplies power to the full-bridge power stage of mosfets and its associated drive, control, and protection circuitry. pvdd can operate from 2.5 v to 5.5 v and must be present to obtain audio output. lowering the pvdd supply results in lower output power and correspondingly lower power consumption. this does not affect audio performance. vdd provides power to the digital logic, analog components, and i/o circuitry. vdd can operate from 1.5 v to 3.6 v and must be provided to obtain audio output. lowering the supply voltage results in lower power consumption, but does not result in lower audio performance. www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 14 of 28 power control the ic starts up in software power-down mode, where all blocks except for the i 2 c interface are disabled. to fully power up the amplifier, clear spwdn (bit 0 of register 0x00). in addition to the software power-down, the software master mute control (m_mute) is enabled at the initial state of the amplifier; therefore, no audio is output until bit 0 of register 0x06 is cleared. the SSM2519 contains a smart power-down feature that, when enabled, analyzes the incoming digital audio and, if the audio is zero for 512 consecutive samples, regardless of sample rate, places the ic in the smart power-down state. in this state, all circuitry except the i 2 s ports are placed in a low power state. after this state is entered, the i 2 s input and master clock (mclk) can be removed to place the part in its lowest power state. when a single nonzero input is received, the SSM2519 leaves this state and resumes normal operation. the SSM2519 can also be powered down to its lowest power state by pulling the sd pin low. power-on reset/voltage supervisor the SSM2519 includes an internal power-on reset and voltage supervisor circuit. this circuit provides an internal reset to all circuitry during initial power-up. it also monitors the power supplies to the ic, mutes the output, and issues a reset when the voltages fall below the minimum operating range. this is done to ensure that no damage occurs due to low voltage operation and that no pops can occur under nearly any power removal condition. a soft reset of the chip can be issued through i 2 c by setting bit 7 of register 0x00 (s_rst). low power modes two low power modes are available. if dac_lpm (bit 5 of register 0x01) is set, the digital-to-analog converter (dac) runs at half speed, reducing the quiescent current. this half speed mode is also active when the mcs setting (bits[4:1] of register 0x00) is set to its lowest value (mcs = 0000) because the slowest acceptable mclk rates can only support half speed dac operation. if amp_lpm (bit 6 of register 0x01) is set, the - modulator runs in a special mode that offers lower quiescent current when the output power is small, at the expense of slightly degraded audio performance. volume control the SSM2519 has a digital volume control. there are 255 levels available, providing a range from +24 db to ?71.25 db in 0.375 db increments. this is a soft volume control, meaning that the gain is adjusted continuously from one value to another. this continuously adjusted gain prevents the audible pop that occurs with an instantaneous gain adjustment. analog gain the SSM2519 has selectable digital and analog gain. selection of these gains occurs via the gain pin. the analog gain settings are optimized for operation at 2.5 v, 3.6 v, 4.2 v, or 5 v pvdd. table 13. gain pin configuration control gain pin configuration analog gain/digital gain tie to vdd 5 v optimized analog/0 db digital gain tie to vdd through 150 k 5 v optimized analog/6 db digital gain tie to vdd through 47 k 4.2 v optimized analog/0 db digital gain tie to vdd through 15 k 3.6 v optimized analog/?3 db digital gain tie to gnd 3.6 v optimized analog/0 db digital gain table 14. special gain case (lr_format tied to vdd through 150 k) gain pin configuration control gain pin configuration analog gain/digital gain tie to vdd 2.5 v optimized analog/?6.75 db digital gain tie to gnd 3.6 v optimized analog/0 db digital gain fault detection and recovery two fault conditions are detected by the SSM2519 fault detection system: overcurrent and overtemperature. when either of these is detected, the amplifier shuts down and a read- only i 2 c bit is set to indicate the cause of the shutdown. the oc and ot fault indicators are bit 6 and bit 5, respectively, of register 0x07. an autorecovery feature can be enabled for temperature faults, current faults, or both, depending on the state of arcv (bits[1:0] of register 0x07). www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 15 of 28 digital audio formats stereo mode 0x02[4:2], sai = 0 (stereo: i 2 s, lj, rj) 0x02[6:5], sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) figure 26. stereo modes: i 2 s, left justified, and right justified tdm, 50% duty cycle mode 0x02[4:2], sai = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels) 0x02[6:5], sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) 0x03[1], bclk_edge = 0 (rising bclk edge used) 0x03[6], lrclk_mode = 0 (50% duty cycl lrclk) 0x03[3:2], slot_width = 0 (32 bclk cycles), 1 (24 bclk cycles), 2 (16 bclk cycles) figure 27. tdm modes with 50% duty cycle lrclk tdm, pulse mode 0x02[4:2], sai = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels) 0x02[6:5], sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) 0x03[1], bclk_edge = 0 (rising bclk edge used) 0x03[6], lrclk_mode = 1 (pulse mode lrclk) 0x03[3:2], slot_width = 0 (32 bclk cycles), 1 (24 bclk cycles), 2 (16 bclk cycles) figure 28. tdm modes with pulse mode lrclk any number bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks left channel right channel right channel left channel right channel left channel bclk lrclk sdata i 2 s sdata lj sdata rj 10750-011 32/24/16 bclks 32/24/16 bclks 32/24/16 bclks channel 1 channel 1 channel 1 channel 2 channel 2 channel 2 channel n channel n channel n 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 24 to 16 bclks 24 or 16 bclks 24 or 16 bclks bclk lrclk sdata i 2 s sdata lj sdata rj 10750-012 32/24/16 bclks 32/24/16 bclks 32/24/16 bclks channel 1 channel 1 channel 1 channel 2 channel 2 channel 2 channel n channel n channel n 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks bclk lrclk sdata i 2 s sdata lj sdata rj 10750-013 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 16 of 28 pcm, multichannel mode 0x02[4:2], sai = 1 (2 channels), 2 (4 channels), 3 (8 channels), 4 (16 channels) 0x02[6:5], sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) 0x03[1], bclk_edge = 1 (falling bclk edge used) 0x03[6], lrclk_mode = 1 (pulse mode lrclk) 0x03[3:2], slot_width = 0 (32 cycles), 1 (24 cycles), 2 (16 cycles) figure 29. multichannel pcm modes pcm, mono mode 0x02[4:2], sai = 5 0x02[6:5], sdata_fmt = 0 (i 2 s), 1 (lj), 2 (rj 24-bit), 3 (rj 16-bit) 0x03[1], bclk_edge = 1 (falling bclk edge used) 0x03[6], lrclk_mode = 1 (pulse mode lrclk) figure 30. mono pcm modes 32/24/16 bclks 32/24/16 bclks 32/24/16 bclks channel 1 channel 1 channel 1 channel 2 channel 2 channel 2 channel n channel n channel n 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks bclk lrclk sdata i 2 s sdata lj sdata rj 10750-014 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks mono channel mono channel mono channel any number bclks bclk lrclk sdata i 2 s sdata lj sdata rj 10750-015 www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 17 of 28 i 2 c configuration interface overview the SSM2519 supports a 2-wire serial (i 2 c-compatible) micro- processor bus driving multiple peripherals. two pins, serial data (sda) and serial clock (scl), carry information between the SSM2519 and the system i 2 c master controller. the SSM2519 is always a slave on the bus, meaning it cannot initiate a data transfer. each slave device is recognized by a unique device address. the device address byte format is shown in figure 31. the address resides in the first seven bits of the i 2 c write. the lsb (bit 7) of this byte sets either a read or write operation. logic level 1 corresponds to a read operation, and logic level 0 corresponds to a write operation. the full byte addresses are shown in figure 31, where the subaddresses are automatically incremented at word boundaries and can be used for writing large amounts of data to contiguous memory locations. this increment happens automatically after a single word write, unless a stop condition is encountered. a data transfer is always terminated by a stop condition. both sda and scl should have a 2.2 k pull-up resistor on the lines connected to them. the device address is 0x70. figure 31. i 2 c device address byte format addressing initially, each device on the i 2 c bus is in an idle state, monitoring the sda and scl lines for a start condition and the proper address. the i 2 c master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while scl remains high. this indicates that an address/data stream follows. all devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the r/ w bit) msb first. the device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this ninth bit is known as an acknowledge bit. all other devices withdraw from the bus at this point and return to the idle condition. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master writes information to the peripheral, whereas a logic 1 means that the master reads information from the peripheral after writing the subaddress and repeating the start address. a data transfer takes place until a stop condition is encountered. a stop condition occurs when sda transitions from low to high while scl is held high. the timing for the i 2 c port is shown in figure 3. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, the SSM2519 immediately jumps to the idle condition. during a given scl high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the SSM2519 does not issue an acknowledge and returns to the idle condition. if the user exceeds the highest subaddress while in auto-increment mode, one of two actions is taken. in read mode, the SSM2519 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. a no acknowledge condition is where the sda line is not pulled low on the ninth clock pulse of scl. if the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the SSM2519 , and the part returns to the idle condition. i 2 c read and write operations figure 33 shows the timing of a single-word write operation. every ninth clock, the SSM2519 issues an acknowledge by pulling sda low. figure 34 shows the timing of a burst mode write sequence. this figure shows an example where the target destination registers are two bytes. the SSM2519 knows to increment its subaddress register every byte because the requested subaddress corresponds to a register or memory area with a byte word length. the timing of a single-word read operation is shown in figure 35. note that the first r/ w bit is 0, indicating a write operation. this is because the subaddress still needs to be written to set up the internal address. after the SSM2519 acknowledges the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the r/ w bit set to 1 (read). this causes the SSM2519 sda to reverse and begin driving data back to the master. the master then responds every ninth pulse with an acknowledge pulse to the SSM2519 . figure 36 shows the timing of a burst mode read sequence. this figure shows an example where the target destination registers are two bytes. the SSM2519 knows to increment its subaddress register at every byte because the requested subaddress corresponds to a register or memory area with a byte word length. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1110000r/w 10750-016 www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 18 of 28 figure 32. i 2 c read/write timing figure 33. single-word i 2 c write format figure 34. burst mode i 2 c write format figure 35. single-word i 2 c read format figure 36. burst mode i 2 c read format scl sda start by master stop by master scl (continued) sda (continued) frame 3 data byte 1 frame 4 data byte 2 frame 1 chip addr ess byte frame 2 subaddress byte ack ack ack ack r/w 10750-017 start bit chip address (7 bits) data byte 1 (8 bits) stop bit r/w = 0 ack by slave subaddress (8 bits) ack by slave 10750-018 data- word 1 data- word 2 r/w = 0 start bit chip address stop bit ack by slave subaddress ack by slave ack by slave ack by slave 10750-019 start bit r/w = 1 chip address data byte 1 stop bit r/w = 0 start bit chip address ack by slave subaddress ack by slave ack by master ack by slave 10750-020 data- word 1 start bit r/w = 1 chip address r/w = 0 start bit chip address stop bit ack by slave subaddress ack by slave ack by master ack by slave 10750-021 www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 19 of 28 register summary table 15. register summary reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 pwr_ctrl [7:0] s_rst reserved no_bclk mcs spwdn 0x05 rw 0x01 sys_ctrl [7:0] hpf_en amp_lpm dac_lpm apwdn_en edge amcs asr 0x30 rw 0x02 sai_fmt1 [7:0] reserved sdata_fmt sai fs 0x02 rw 0x03 sai_fmt2 [7:0] bclk_gen lrclk_mode lrclk_pol sai_msb slot_width bclk_edge reserved 0x00 rw 0x04 ch_sel [7:0] reserved ch_sel 0x00 rw 0x05 vol_ctrl [7:0] vol 0x40 rw 0x06 gain_ctrl [7:0] amute reserved ana_gain reserved m_mute 0x11 rw 0x07 fault_ctrl1 [7:0] reserved oc ot mrcv max_ar arcv 0x0c rw www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 20 of 28 register details software reset and master softwa re power-down control register address: 0x00, reset: 0x05, name: pwr_ctrl table 16. bit descriptions for pwr_ctrl bits bit name settings description reset access 7 s_rst software reset. the software reset bit resets all internal blocks, including i 2 c registers, to their default states. 0x0 rw 0 normal operation 1 software reset 6 reserved reserved. 0x0 rw 5 no_bclk no bclk operational mode . mclk also used as bclk. 0x0 rw 0 bclk used as bclk 1 mclk used as bclk. no signal needed on bclk pin. [4:1] mcs master clock select. mcs must be set according to the input mclk ratio relative to the input sample frequency. refer to table 10. 0x2 rw 0000 64 f s mclk 0001 128 f s mclk 0010 256 f s mclk 0011 384 f s mclk 0100 512 f s mclk 0101 768 f s mclk 0110 100 f s mclk 0111 200 f s mclk 1000 400 f s mclk 1001 reserved 0 spwdn master software power-down. software power-down puts all blocks except the i 2 c interface in a low power state. 0x1 rw 0 normal operation 1 software master power-down www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 21 of 28 edge speed, power, and cl ocking control register address: 0x01, reset: 0x30, name: sys_ctrl table 17. bit descriptions for sys_ctrl bits bit name settings description reset access 7 hpf_en dc blocking high-pass filter enable. the SSM2519 contains a selectable high-pass filter. the ?3 db frequency is at 6 hz with a 48 khz sample rate. this frequency increases linearly with lower sample rates. 0x0 rw 0 high-pass filter off 1 high-pass filter on 6 amp_lpm amplifier low power mode. 0x0 rw 0 normal operation 1 low power (return to zero) class-d mode 5 dac_lpm dac low power mode. 0x1 rw 0 normal operation 1 low power operation mode. dac runs at half speed. 4 apwdn_en auto power-down enable. auto power-down automatically puts the ic in a low power state when 2048 consecutive zero input samples have been received. 0x1 rw 0 auto power-down disabled 1 auto power-down enabled [3:2] edge edge rate control. this controls the edge speed of the power stage. the low emi operation mode reduces the edge speed, lowering emi and power efficiency. 0x0 rw 00 normal operation 01 lower emi mode operation 10 lower emi mode operation 11 lowest emi mode operation 1 amcs auto mclk select. 0x0 rw 0 master clock rate determined by mcs bits in register 0x00 1 master clock rate automatically detected 0 asr autosample rate. 0x0 rw 0 sample rate setting determined by fs bit in register 0x02 1 autosample and mclk rate detection enabled www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 22 of 28 serial audio interface and sa mple rate control register address: 0x02, reset: 0x02, name: sai_fmt1 table 18. bit descriptions for sai_fmt1 bits bit name settings description reset access 7 reserved reserved. 0x0 rw [6:5] sdata_fmt serial data format. 0x0 rw 00 i 2 s, bclk delay by 1 01 left justified 10 right justified 24-bit data 11 right justified 16-bit data [4:2] sai serial audio interface format. 0x0 rw 000 stereo: i 2 s, lj, rj 001 tdm2 010 tdm4 011 tdm8 100 tdm16 101 mono pcm 110 reserved 111 reserved [1:0] fs sample rate selection. 0x2 rw 00 8 khz to 12 khz 01 16 khz to 24 khz 10 32 khz to 48 khz 11 reserved www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 23 of 28 serial audio interface control register address: 0x03, reset: 0x00, name: sai_fmt2 table 19. bit descriptions for sai_fmt2 bits bit name settings description reset access 7 bclk_gen bclk internal generation. when bclk _gen is enabled, an internally generated bclk is used. therefore, routing the bclk signal to the pin is not required. 0x0 rw 0 external bclk used 1 internally generated bclk used 6 lrclk_mode lrclk mode selection for tdm operation. 0x0 rw 0 50% duty cycle lrclk 1 pulse mode lrclk 5 lrclk_pol lrclk polarity control. 0x0 rw 0 normal lrclk operation 1 inverted lrclk operation 4 sai_msb sdata bit stream order. 0x0 rw 0 msb first sdata 1 lsb first sdata [3:2] slot_width bclk cycles per frame in tdm modes select. 0x0 rw 00 32 bclk cycles per slot 01 24 bclk cycles per slot 10 16 bclk cycles per slot 11 reserved 1 bclk_edge bclk active edge select. 0x0 rw 0 rising bclk edge used 1 falling bclk edge used 0 reserved reserved. 0x0 rw www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 24 of 28 channel mapping control register address: 0x04, reset: 0x00, name: ch_sel note that not all the settings of ch_sel are available in all serial interface modes. for example, in stereo and tdm2 modes, only setting 0000 (channel 0) and setting 0001 (channel 1) are valid because these modes can only contain two channels. in tdm4, setting 0000 to setting 0011 are supported. in tdm8, setting 0000 to setting 0111 are supported. in tdm16, setting 0000 to setting 1111 are supported. table 20. bit descriptions for ch_sel bits bit name settings description reset access [7:4] reserved reserved. 0x0 rw [3:0] ch_sel channel mapping select. select input sdata channel to map to left channel output. 0x0 rw 0000 channel 0 from sai to output 0001 channel 1 from sai to output 0010 channel 2 from sai to output 0011 channel 3 from sai to output 0100 channel 4 from sai to output 0101 channel 5 from sai to output 0110 channel 6 from sai to output 0111 channel 7 from sai to output 1000 channel 8 from sai to output 1001 channel 9 from sai to output 1010 channel 10 from sai to output 1011 channel 11 from sai to output 1100 channel 12 from sai to output 1101 channel 13 from sai to output 1110 channel 14 from sai to output 1111 channel 15 from sai to output www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 25 of 28 volume control register address: 0x05, reset: 0x40, name: vol_ctrl table 21. bit descriptions for vol_ctrl bits bit name settings description reset access [7:0] vol volume control. 0x40 rw 00000000 +24 db 00000001 +23.625 db 00000010 +23.35 db 00000011 +22.875 db 00000100 +22.5 db 00000101 decreasing in 0.375 db steps 00111111 +0.375 db 01000000 0 01000001 ?0.375 db 01000010 decreasing in 0.375 db steps 11111101 ?70.875 db 11111110 ?71.25 db 11111111 mute www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 26 of 28 gain and mute control register address: 0x06, reset: 0x11, name: gain_ctrl table 22. bit descriptions for gain_ctrl bits bit name settings description reset access 7 amute automatic mute enable. when the automatic mute function is enabled, after 2048 consecutive zero input samples have been received, the outputs are automatically muted. 0x0 rw 0 automute enabled 1 automute disabled 6 reserved reserved. 0x0 rw [5:4] ana_gain analog gain control. this controls the analog gain of the class-d modulator. there are two settings optimized for 3.6 v operation from a lithium ion battery and for 5 v operation. 0x1 rw 00 2 v gain 01 3.6 v gain 10 4.2 v gain 11 5 v gain [3:1] reserved reserved. 0x0 rw 0 m_mute master mute control. setting the master mute control bit soft-mutes both channels. 0x1 rw 0 normal operation 1 master mute www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet SSM2519 rev. 0 | page 27 of 28 fault control register address: 0x07, reset: 0x0c, name: fault_ctrl1 table 23. bit descriptions for fault_ctrl1 bits bit name settings description reset access 7 reserved reserved. 0x0 rw 6 oc overcurrent fault. 0x0 r 0 normal operation 1 overcurrent fault 5 ot overtemperture fault status. 0x0 r 0 normal operation 1 overtemperature fault 4 mrcv manual fault recovery. 0x0 w 0 normal operation 1 writing logic 1 causes a manual fault recovery attempt when arcv = 11 [3:2] max_ar maximum fault recovery attempts. the maximum automatic fault recovery bit determines how many attempts at autorecovery are performed. 0x3 rw 00 one autorecovery attempt 01 three autorecovery attempts 10 seven autorecovery attempts 11 unlimited autorecovery attempts [1:0] arcv autofault recovery control. 0x0 rw 00 autofault recovery for overtemperature and overcurrent faults 01 autofault recovery for overtemperature fault only 10 autofault recovery for overcurrent fault only 11 no autofault recovery www.datasheet.net/ datasheet pdf - http://www..co.kr/
SSM2519 data sheet rev. 0 | page 28 of 28 outline dimensions figure 37. 12-ball wafer level chip scale package [wlcsp] (cb-12-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding SSM2519acbz-r7 ?40c to +85c 12-ball wafer level chip scale package [wlcsp] cb-12-6 y4b SSM2519acbz-rl ?40c to +85c 12-ball wafer level chip scale package [wlcsp] cb-12-6 y4b eval-SSM2519z evaluation board 1 z = rohs compliant part. a b c d 0 .560 0 .500 0 .440 1.455 1.415 1.375 1.705 1.665 1.625 12 3 bottom view (ball side up) top view (ball side down) end view 0.300 0.260 0.220 1.20 ref 0.80 ref 0.40 bsc ball a1 identifier 05-16-2012-a seating plane 0.230 0.200 0.170 coplanarity 0.05 ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10750-0-7/12(0) www.datasheet.net/ datasheet pdf - http://www..co.kr/

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